1. Field of Invention
The present invention relates to a method for fabricating a semiconductor wafer. More particularly, the present invention relates to a method for fabricating alignments marks on a semiconductor wafer, wherein alignment performance is enhanced.
2. Description of Related Art
The fabrication of semiconductor devices on a semiconductor wafer involves a transfer of a succession of patterns from photo masks onto the wafer. In order for the devices to perform properly, each circuit pattern must be formed aligning as precisely as possible with the circuit pattern that has been previously formed on the wafer. In other words, the overlay error must be minimized.
One alignment technique is known as the through-the-lens (TTL) alignment. The TTL alignment is characterized in that the alignment of a reticle or a mask and the wafer is effected through a projection optical system. The TTL alignment is achieved by illuminating the alignment marks on a reticle using a light source (for example, a 633 nm laser light), wherein each reticle alignment mark is composed of a series of parallel lines with a pitch. The image of the reticle alignment mark is projected by the projection optical system onto the wafer bearing alignment marks having similar alignment patterns of the reticle alignment mark. Portions of the light which are incident on the alignment pattern of the wafer alignment mark are reflected and detected. The portions of the light which are incident on the lines of the wafer alignment mark are strongly reflected, while the portions of the light that are incident between the lines are weakly reflected. Optimum alignment occurs when the alignment pattern on the reticle is properly aligned with the alignment pattern on the wafer. Typically, a minimum of two alignment marks is defined on each wafer, although increasing the number of alignment marks increases the alignment accuracy. However, the presence of these marks on the wafer reduces the available area for semiconductor elements. The increase of alignment marks for increasing the alignment accuracy is thereby hindered.
Alternatively, alignment marks, known as the ATHENA (Advanced Technology using High order Enhancement of Alignment) marks, are formed in the scribe line area provided between chips. In the ATHENA alignment technique, light is radiated onto the wafer. The radiated light is diffracted by the alignment marks, and the diffraction pattern is detected. The relative position of the wafer and the photomask is then adjusted accordingly. The quality of the diffracted light from the alignment mark is a directly related to the structure of the alignment mark, such as the material or the dimension of the mark. Since the alignment marks are formed in the scribe line area, there will be no unwanted loss of dies. Further, additional alignment marks may form per wafer, for example, two marks per shot or 8 to 18 marks per wafer, to improve the alignment accuracy.
Typically, each alignment mark comprises a topographical pattern, such a plurality of grooves and lands, which can be formed by, for example etching a controlled depth into wafer. The etching of the wafer creates a step height in the wafer. Once the alignment mark is formed on a wafer, it will be used for position detection in subsequent processes. However as the wafer has undergone various processes of forming circuit patterns thereon, the integrity of the alignment mark on the wafer is compromised. For example, some of the intermediate processing steps of forming circuit patterns on the wafer, such as chemical mechanical polishing (CMP) or deposition of thick or opaque layer, can damage or distort the alignment marks on the wafer or bury the marks under opaque layers.
When a chemical mechanical polishing (CMP) process, which is planarization technique, is performed to planarize a dielectric layer, not only the dielectric layer over the semiconductor element area is planarized, the dielectric layer over the alignment mark in the scribe line area is also planarized. Accordingly, the step height of the alignment mark is destroyed. If polysilicon or metal silicide or metal layers, which are opaque, are further formed thereon, the alignment mark will become invisible.
When the alignment mark has low reflectivity and small step height, the mark is difficult to be detected. Further, since additional layers may have deposited on the mark, the reading of the mark is interfered, for example the contrast of the image of the mark is poor and the reading of the image is noisy.